Researchers discovered undocumented SDR capabilities in ESP32 microcontrollers, enabling raw IQ baseband sample capture across 2.2–2.7 GHz and 4.8–6.0 GHz bands. Multiple independent projects leveraged this feature for spectrum analysis, direction finding, and FPV video reception, with the ESP32-S31 enabling continuous streaming via Gigabit Ethernet.
Orthogone offers a high-performance 10G TCP/UDP/IP FPGA core with 6.2ns ultra-low latency for financial trading, HPC, and networking applications. The core supports layers 2-4 protocols and is available in multiple versions with flexible integration options.
A developer describes building a custom FPGA-based TPU for matrix operations, progressing from a Zynq board to a smaller KC705 with VexRiscv CPU and 4×4 int8 cores. The system compiles JAX programs to C, running compute-intensive operations on the arrays while keeping loops on the CPU, achieving 104 ms inference on MNIST classification.
Project Cyan is a clean-sheet hardware implementation of an SGI IP20 system, recreating a 64-bit MIPS III processor and full system integration including SCSI, Ethernet, graphics, and memory subsystems. The project uses synthesizable modules tested against original diagnostics, FPGA builds, and full-system simulation to preserve exact hardware behavior and fix production RTL.