A hobbyist designed a TPU and optimized transformer inference on a $100 Cmod A7 FPGA board, implementing a small transformer model to predict the next token in addition sequences. The project analyzes ML performance through compute and memory communication bottlenecks, using matrix multiplications as the core workload with simplified operations like ReLU activation for hardware feasibility.
Gherkin Labs reverse engineered Google's TPU communication protocol and built a simulator that runs unmodified TPU software, enabling cycle-level performance tracing without access to actual hardware. The simulator, deployed as a shared library, decodes instruction streams and simulates tensor and sparse cores on CPU, addressing the lack of public TPU documentation to improve ML efficiency and enable better kernel optimization.