SiFive and AMD demonstrated AMD ROCm running on SiFive's BigSky Datacenter Development Platform, showcasing the Gemma4-E2B LLM model with SiFive P870-D CPUs and AMD Radeon AI PRO R9700 GPUs. The collaboration aims to optimize ROCm on RISC-V powered servers to accelerate datacenter AI compute workloads.
A 172-line RISC-V RV32I emulator written in Nix executes real machine-code instructions during Nix evaluation, supporting integer arithmetic, branching, memory operations, and minimal I/O without external dependencies. The emulator includes sample programs like hello and fibonacci assembled with GNU binutils, with machine-code images provided as JSON arrays for direct execution.
RVVTS is an open-source, modular framework for comprehensive testing of RISC-V Vector implementations and other RISC-V extensions. The framework automates test generation, execution, coverage measurement, and failure analysis using techniques like instruction isolation and code minimization, and has uncovered bugs in multiple RISC-V implementations including PULP Ara, Sail-RISC-V, RISC-V VP++, and QEMU.
Infineon presented its RISC-V strategy for automotive microcontrollers at Hot Chips 2026, emphasizing zone architecture consolidation that balances real-time control loops with centralized compute for ADAS and vehicle management. RISC-V offers scalability, avoids vendor lock-in, and enables heterogeneous workloads across safety-critical automotive systems through standardized profiles and virtualization support.
Pi-box is an Electron app that runs a coding agent in a fully sandboxed WebAssembly environment by combining container2wasm, TinyEmu, and RISC-V emulation. The project uses a custom JavaScript TCP/IP stack and filesystem implementation to enable networking and host mounts without external dependencies, making it portable across platforms despite performance trade-offs.
Dave Ditzel, founder of Esperanto Technologies, presented the company's journey from custom ISA to RISC-V adoption, detailing the ET-SoC-1 manycore processor with over 1,000 RISC-V cores optimized for AI and HPC workloads. The keynote traced decades of processor architecture development and outlined how Esperanto's technology is transitioning to open-source platforms through CORE-ET and AIFoundry's ET Platform.
A repository containing a RISC-V instruction set emulator with Linux kernel support, including an rv32ima emulator, minimal device emulation, build configurations for a custom Linux kernel, device tree definitions, and init programs needed to boot a complete Linux system from scratch.
NextSilicon, led by Elad Raz, built Arbel, a high-performance RISC-V CPU core designed to complement its Maverick acceleration platform for HPC and AI workloads. The author, a former Intel processor architect with 18 years of experience, describes the technical and human challenges of assembling a specialized team to build a competitive CPU from scratch using a novel software-defined hardware approach.
Canonical presented how Ubuntu is being adapted for enterprise RISC-V systems at Hot Chips 2026, emphasizing that Ubuntu should behave consistently across all processor architectures. The company manages this through standardized baselines, package support across 30,000+ packages, and architecture variants that enable optimization while maintaining long-term support and security guarantees. Canonical targets the RVA23 profile for RISC-V with server-class hardware expected from multiple vendors in 2026-2027.