# HBM demand — X 热门讨论 (2026-09-10 14:23 UTC)
## @PhotonCap (Photon Capital) · 09-10 05:41 · ♥31 ↻2 💬2 - Teradyne ($TER) CEO Greg Smith said at the Goldman Sachs Communacopia + Technology Conference on September 9 that AI has become a central growth driver for the company's semiconductor test business.
> The key point is that AI is not simply creating demand for more chips. It is increasing the amount of testing required per chip, as advanced nodes, chiplets, HBM and CPO all raise test intensity.
> The CPO numbers are particularly interesting. A potential increase in test-equipment TAM from $100M in 2026 to as much as $700M in 2028 reinforces the view that manufacturing test and optical alignment could become important bottlenecks as CPO moves toward volume production.
> $TER's AI exposure is therefore becoming much broader than GPUs alone. AI ASICs, networking, HBM/DRAM, SSDs, Silicon Photonics/CPO and system-level burn-in increasingly connect $TER to multiple layers of the AI infrastructure buildout.
> I think looking at this only as a $TER story is too narrow. The bigger AI-driven shift is a structural increase in test, inspection, metrology, probing, burn-in and packaging equipment intensity across semiconductor manufacturing, not simply market-share gains for one tester vendor.
> As GPUs and custom ASICs become larger and more complex, and as chiplets, HBM, advanced packaging and CPO are added, the number of things that must be verified from wafer level through package and system-level test increases materially. The more expensive the device, the more costly it becomes to discover yield or reliability problems late in the process, which can support higher equipment intensity across both front-end and back-end manufacturing.
> That is why I think investors should look beyond $TER to names such as $FORM in probing, $AEHR in burn-in and wafer-level reliability testing, as well as inspection/metrology and advanced-packaging equipment suppliers. The next derivative of AI CapEx may come not just from producing more compute chips, but from the need to test increasingly complex chips more often and with much greater precision.
> CPO and multi-die packages make this even more important because electrical test alone is no longer sufficient. Optical alignment, known-good-die screening, thermal and reliability testing, and package-level characterization expand the testing surface, which is why I would view the broader equipment chain as an increasingly important AI infrastructure sub-theme. https://x.com/PhotonCap/status/2097923273401176471